Semiconductor device

ABSTRACT

A semiconductor device is disclosed that includes an insulation substrate, a metal wiring layer, a semiconductor element, a heat sink, and a stress relaxation member located between the insulation substrate and the heat sink. The heat sink has a plurality of partitioning walls that extend in one direction and are arranged at intervals. The stress relaxation member includes a stress absorbing portion formed by through holes extending through the entire thickness of the stress relaxation member. Each hole is formed such that its dimension along the longitudinal direction of the partitioning walls is greater than its dimension along the arranging direction of the partitioning walls.

This application is a divisional of U.S. application Ser. No. 12/496,391filed on Jul. 1, 2009 entitled “Semiconductor Device”, which isincorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a semiconductor device in which aninsulation substrate and a heat sink are coupled to each other such thatheat can be conducted therebetween.

BACKGROUND

Semiconductor devices have been known that have an insulation substratemade of, for example, aluminum nitride, front and back metal plates madeof pure aluminum, a semiconductor element joined to the front metalplate by, for example, soldering, a heat sink serving as a heatradiating device joined to the back metal plate. The metal plates arejoined to each of the front and back surfaces of the insulationsubstrate. The heat sink is coupled to the back metal plate to bethermally conductive with the back metal plate. The heat sink radiatesheat generated by the semiconductor element. The above describedsemiconductor devices are required to maintain heat radiatingperformance of the heat sink for an extended period of time. However,depending on the use conditions, thermal stress is generated by thedifference in coefficient of linear expansion between the insulationsubstrate, the metal plates, and the heat sink of the conventionalconfiguration. This can cause joint portions to crack and warp, loweringthe heat radiating performance of the heat sink.

To eliminate such a drawback, Japanese Laid-Open Patent Publication No.2003-17627 discloses a semiconductor module having thermal stressrelaxation portions on the back metal plate. The thermal stressrelaxation portions are formed by steps, grooves, or recesses that havea predetermined depth. The number and the size of the thermal stressrelaxation portions are determined such that the volume ratio of theback metal plate to the front metal plate is not more than 0.6.

Japanese Laid-Open Patent Publication No. 2007-173405 discloses asemiconductor module in which, on a joint surface of the back metalplate with the heat sink, a non-joint region formed by holes or groovesand a joint region where no holes or grooves are formed. The area of thejoint region is set to be 65% to 85% of the entire joint surface of theback metal plate.

In the semiconductor module disclosed in Japanese Laid-Open PatentPublication No. 2003-17627, the steps, grooves, or recesses, which serveas thermal stress relaxation portions formed on the back metal plate,relax thermal stress generated in the semiconductor module when thetemperature changes. Thus, in order to increase the thermal stressrelaxing performance, the steps, grooves, or recesses are preferably aslarge as possible. However, increasing the size of the steps, grooves,or recesses, in turn, reduces the joint area between the back metalplate and the heat sink. This reduces the thermal conductivity of theback metal plate. Thus, the balance between the thermal conductivity andthe thermal stress relaxing performance needs to taken intoconsideration. That is, the larger the steps, grooves, or the recessesforming thermal stress relaxation portions, the lower the heat radiationefficiency becomes. Thus, there is a limit to improvement of the stressrelaxation performance.

Likewise, according to the semiconductor module disclosed in JapaneseLaid-Open Patent Publication No. 2007-173405, the larger the non-jointregion, the lower the thermal conductivity of the back metal plate ofthe semiconductor module becomes. This puts a limit on improvement ofthe stress relaxation performance.

Particularly, in the case of a semiconductor device such as a powermodule, on which a semiconductor element generating a great amount ofheat is mounted, there is a demand for improving the function to relaxthe thermal stress generated in the semiconductor device withoutlowering the heat radiation efficiency. Japanese Laid-Open PatentPublication No. 2004-6717 discloses a power semiconductor device thatincludes an insulation substrate, front and back metal plates (lowthermal expansion coefficient metal plates) joined to each of the frontand back surfaces of the insulation substrate, a power semiconductorelement joined to the front surface of the front metal plate by, forexample, soldering, and a heat sink coupled to the back metal plate tobe thermally conductive with the back metal plate. The back metal platehas a linear expansion coefficient that is of the same order of thelinear expansion coefficients of the power semiconductor element and theinsulation substrate. The heat sink has a plurality of partitioningwalls defined by a plurality of grooves formed in the heat sink. Thepartitioning walls are arranged in regions that correspond to theinsulation substrate. The distal end of each partitioning wall is notfixed. Thus, the rigidity of the heat sink of the power semiconductordevice disclosed in the publication is lower than that of a heat sink inwhich the distal ends of partitioning walls are fixed. Therefore,thermal stress generated in the heat sink and the insulation substrateis reduced by deformation of the heat sink. However, since thepartitioning walls are arranged only in a region that corresponds to theinsulation substrate through the low thermal expansion coefficient metalplates, the rigidity of the heat sink cannot be made sufficiently low.The heat sink therefore cannot sufficiently reduce thermal stress. Also,Japanese Laid-Open Patent Publication No. 2004-6717 discloses astructure in which partition walls with free distal ends are providedbelow a region to which the low thermal expansion coefficient metalplates are not joined. However, since the partitioning walls with freedistal ends reduce the rigidity of the heat sink, the rigidity of theheat sink, which has a greater widthwise length than that of the lowthermal expansion coefficient metal plates, may be lowered below theminimum rigidity required for the heat sink.

Further, Japanese Laid-Open Patent Publication No. 5-299549 discloses aheat transfer cooling device that includes a box and a plurality ofpartitioning walls. The partitioning walls define a plurality of flowpassages in the box. The partitioning walls are arranged along thediagonals of the base of the box, such that the space between adjacentpartitioning walls is reduced toward the diagonals. In the heat transfercooling device disclosed in Japanese Laid-Open Patent Publication No.5-299549, spaces between adjacent partitioning walls are smaller in acentral part of the heat transfer cooling device, where the temperatureeasily rises, so that the number of the partitioning walls is increasedin the central part. Thus, the heat radiation efficiency at the centralpart of the cooling device is higher than that in the other parts.

However, in the heat transfer cooling device of Japanese Laid-OpenPatent Publication No. 5-299549, since a plurality of partitioning wallsare arranged from one corner of the cooling device toward another cornerat predetermined intervals, the rigidity of the cooling device isincreased. Therefore, when the temperature of the heat transfer coolingdevice changes, the device cannot exert sufficient stress relaxationperformance.

Accordingly, it is an objective of the present invention to provide asemiconductor device that is excellent in heat radiating performance andreliably relaxes stress. Another objective of the present invention isto provide a semiconductor device that prevents the rigidity of a heatsink from being lowered.

To achieve the foregoing objective and in accordance with a first aspectof the present invention, a semiconductor device including an insulationsubstrate, a metal wiring layer, a semiconductor element, a heat sink,and a stress relaxation member is provided. The insulation substrate hasa first surface and a second surface that is opposite to the firstsurface. The metal wiring layer is joined to the first surface of theinsulation substrate. The semiconductor element is joined to the metalwiring layer. The heat sink is arranged on the second surface of theinsulation substrate. The stress relaxation member is made of a materialhaving a high thermal conductivity. The stress relaxation member islocated between the insulation substrate and the heat sink in suchmanner as to couple the insulation substrate and the heat sink such thatheat can be conducted therebetween. The heat sink has a plurality ofpartitioning walls that extend in one direction and are arranged atintervals. The stress relaxation member has a stress absorbing portionthat is formed by a hole. The hole either extends through the entirethickness of the stress relaxation member or opens in one of bothsurfaces in the direction of the thickness. The hole is formed such thatits dimension along the longitudinal direction of the partitioning wallsis greater than its dimension along the arranging direction of thepartitioning walls.

In accordance with a second aspect of the present invention, asemiconductor device including an insulation substrate, a metal wiringlayer, a semiconductor element, a heat sink, and a stress relaxationmember is provided. The insulation substrate has a first surface and asecond surface that is opposite to the first surface. The metal wiringlayer is joined to the first surface of the insulation substrate. Thesemiconductor element is joined to the metal wiring layer. The heat sinkis arranged on the second surface of the insulation substrate. Thestress relaxation member is made of a material having a high thermalconductivity. The stress relaxation member is located between theinsulation substrate and the heat sink in such manner as to couple theinsulation substrate and the heat sink such that heat can be conductedtherebetween. The heat sink has a plurality of partitioning walls thatextend in one direction and are arranged at intervals. The stressrelaxation member has a stress absorbing portion. The stress absorbingportion includes a plurality of groups of through holes extendingthrough the entire thickness of the stress relaxation member. Thethrough holes are arranged along the longitudinal direction of thepartitioning walls. Each of all the through holes is formed such thatits opening dimension along the arranging direction of the partitioningwalls is greater than its opening dimension along the longitudinaldirection of the partitioning walls. In each of the groups of throughholes, the sum of the opening dimensions of the through holes along thelongitudinal direction of the partitioning walls is longer than themaximum width of the stress absorbing portion along the arrangingdirection of the partitioning walls.

In accordance with a third aspect of the present invention, asemiconductor device including an insulation substrate, a first metalplate, a semiconductor element, a second metal plate, and a heat sink isprovided. The insulation substrate has a first surface and a secondsurface that is opposite to the first surface. The first metal plate isjoined to the first surface of the insulation substrate. Thesemiconductor element is joined to the first metal plate. The secondmetal plate is joined to the second surface of the insulation substrate.The heat sink cools the semiconductor element, and is coupled to thesecond metal plate such that heat can be conducted. The heat sinkincludes a case portion and a plurality of partitioning walls located inthe case portion. The partitioning walls define a plurality of coolingmedium passages. The case portion has a surface that faces the secondmetal plate, which surface includes a joint region, to which the secondmetal plate is joined, and a non-joint region, to which the second metalplate is not joined. Each partitioning wall includes a first end facingthe second metal plate and a second end opposite to the first end. Thepartitioning walls include first partitioning walls and secondpartitioning walls. The first end of each first partitioning wall isjoined to an inner surface of the case portion. The second end of eachfirst partitioning wall is not joined to an inner surface of the caseportion. The first and second ends of each second partitioning wall arejoined to inner surfaces of the case portion. Among the first and secondpartitioning walls, at least one or more of the first partitioning wallspass through a region in the case portion that corresponds to the jointregion. Among the first and second partitioning walls, only one or moreof the second partitioning walls pass through a region in the caseportion that corresponds to the non-joint region.

In accordance with a fourth aspect of the present invention, asemiconductor device including an insulation substrate, a first metalplate, a semiconductor element, a second metal plate, and a heat sink isprovided. The insulation substrate has a first surface and a secondsurface that is opposite to the first surface. The first metal plate isjoined to the first surface of the insulation substrate. Thesemiconductor element is joined to the first metal plate. The secondmetal plate is joined to the second surface of the insulation substrate.The heat sink cools the semiconductor element, and is coupled to thesecond metal plate such that heat can be conducted. The heat sinkincludes a case portion and a plurality of partitioning walls located inthe case portion. The partitioning walls define a plurality of coolingmedium passages. All the partitioning walls are located in a region inthe case portion that is directly below the semiconductor element.

Other aspects and advantages of the present invention will becomeapparent from the following description, taken in conjunction with theaccompanying drawings, illustrating by way of example the principles ofthe invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with objects and advantages thereof, may best beunderstood by reference to the following description of the presentlypreferred embodiments together with the accompanying drawings in which:

FIG. 1 is a schematic cross-sectional view illustrating a semiconductordevice according to a first embodiment of the present invention;

FIG. 2 is a schematic plan view of the semiconductor device shown inFIG. 1;

FIG. 3A is a schematic partial plan view illustrating a semiconductordevice according to a modification of the first embodiment;

FIG. 3B is a schematic partial plan view illustrating a semiconductordevice according to a modification of the first embodiment;

FIG. 3C is a schematic partial plan view illustrating a semiconductordevice according to a modification of the first embodiment;

FIG. 4 is a schematic cross-sectional view illustrating a semiconductordevice according to a second embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view taken along line 5-5 in FIG.4.

FIG. 6 is a schematic cross-sectional view illustrating a semiconductordevice according to a modification of the second embodiment;

FIG. 7 is a schematic cross-sectional view illustrating a semiconductordevice according to a modification of the second embodiment;

FIG. 8 is a schematic cross-sectional view illustrating a semiconductordevice according to a third embodiment of the present invention;

FIG. 9 is a schematic plan view of the semiconductor device shown inFIG. 8;

FIG. 10A is a schematic partial cross-sectional view illustratingpartitioning walls of a semiconductor device according to a modificationof the third embodiment; and

FIG. 10B is a schematic partial cross-sectional view illustratingpartitioning walls of a semiconductor device according to a modificationof the third embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A first embodiment of the present invention will now be described withreference to FIGS. 1 to 3C. Each of the FIGS. 1 to 3C schematicallyshows the structure of a semiconductor device 10A according to the firstembodiment. For the illustrative purposes, the dimensions of some of theelements are exaggerated. That is, the ratios of the widths, lengths,and thicknesses of some of the elements of the semiconductor device 10Ain the drawings are not to scale. The semiconductor device 10A ismounted on a vehicle.

As shown in FIG. 1, the semiconductor device 10A includes a circuitsubstrate 11, a semiconductor element (semiconductor chip) 12 mounted onthe circuit substrate 11, a heat sink 16, and a stress relaxation member20 located between the circuit substrate 11 and the heat sink 16. Thecircuit substrate 11 includes a ceramic substrate 13, which is aninsulation substrate, a first metal plate (a metal circuit board) joinedto a front surface 13 a (a first surface) of the ceramic substrate 13,and a second metal plate 15 joined to a back surface 13 b (a secondsurface) of the ceramic substrate 13. The first metal plate 14 and thesecond metal plate 15 are made of, for example, aluminum or copper.

The upper surface of the ceramic substrate 13 as viewed in FIG. 1 is thefront surface 13 a, on which the semiconductor element 12 is mounted.Also, the first metal plate 14, which serves as a wiring layer, isjoined to the front surface 13 a. The semiconductor element 12 is joinedto the first metal plate 14 with solder, which is not illustrated. Thesemiconductor element 12 is, for example, an IGBT (Insulated GateBipolar Transistor), a MOSFET, or a diode.

The second metal plate 15 is joined to the lower surface of the ceramicsubstrate 13 as viewed in FIG. 1, or the back surface 13 b. The secondmetal plate 15 functions as a coupling layer for coupling the ceramicsubstrate 13 and the heat sink 16 to each other.

The heat sink 16 is made of metal and functions as a forced-coolingcooler that forcibly removes heat generated in the semiconductor element12. The cooling capacity of the heat sink 16 is set such that, when thesemiconductor element 12 is steadily generating heat (a normal state),the heat generated in the semiconductor element 12 is conducted to theheat sink 16 via the circuit substrate 11, and as a result, the heat issmoothly removed. The heat sink 16 is formed to be rectangular in aplanar view, such that the longitudinal direction of the heat sink 16corresponds to arrow direction X in FIG. 2, and the transverse directionof the heat sink 16 corresponds to arrow direction Y in FIG. 2. Theouter shell of the heat sink 16 is formed by a hollow flat case portion17.

A plurality of partitioning walls 18 are provided in the case portion17. The partitioning walls 18 linearly extend along the transversedirection of the heat sink 16, that is, along arrow direction Y in FIG.2. As shown in FIGS. 1 and 2, the partitioning walls 18 are arrangedalong the longitudinal direction of the heat sink 16, or in arrowdirection X of FIG. 2, at equal intervals, and extend parallel with eachother. Adjacent pairs of the partitioning walls 18, and the outermostpartitioning walls 18 and inner wall surfaces 17 c of the case portion17 define cooling medium passages 19, through which fluid (for example,cooling water) flows. The stress relaxation member 20 is located betweenthe heat sink 16 and the second metal plate 15 of the circuit substrate11. The stress relaxation member 20 couples the circuit substrate 11 andthe heat sink 16 to each other.

The stress relaxation member 20 is made of a material having a highthermal conductivity. In this embodiment, the stress relaxation member20 is made of aluminum. The stress relaxation member 20 is formed into aflat plate that is rectangular in a planar view. A first surface 20 a ofthe stress relaxation member 20 is entirely brazed to the second metalplate 15, and a second surface 20 b is entirely brazed to the heat sink16. That is, joint portions made of brazing filler metal are formedbetween the stress relaxation member 20 and the second metal plate 15and between the stress relaxation member 20 and the heat sink 16. Thus,the circuit substrate 11 and the heat sink 16 are coupled to each othersuch that heat can be conducted therebetween via the stress relaxationmember 20. Heat generated in the semiconductor element 12 is conductedto the heat sink 16 via the circuit substrate 11 and the stressrelaxation member 20 in this order. Also, the stress relaxation member20 has through holes 21, the number of which is twelve in thisembodiment. The through holes 21 function as stress absorbing portionsand extend through the stress relaxation member 20 only along thethickness. Each through hole 21 has an elliptic shape in a planar view.

The through holes 21 are formed by pressing (machining) a flat platethat constitutes the stress relaxation member 20. As shown in FIG. 2;each through hole 21 is formed such that a dimension T1 along thelongitudinal direction of the partitioning walls 18, or along arrowdirection Y, is greater than a dimension T2 along the direction in whichthe partitioning walls 18 are arranged (arranging direction), or alongarrow direction X in FIGS. 1 and 2. All the through holes 21 have thesame shapes. Two or more of the through holes 21 are arranged along thelongitudinal direction of the partitioning walls 18, or along arrowdirection Y. The major axis of each through hole 21 extends parallelwith the longitudinal direction of the partitioning walls 18, and theminor axis of each through hole 21 extends parallel with the arrangingdirection of the partitioning walls 18. Therefore, the stress relaxationmember 20 is more easily deformed along the longitudinal direction ofthe partitioning walls 18 than along the arranging direction of thepartitioning walls 18. The through holes 21 are symmetrical with respectto a reference point P on the stress relaxation member 20, whichreference point P corresponds to the center of the semiconductor element12. No through hole 21 is formed in a part of the stress relaxationmember 20 that is directly below the semiconductor element 12. That is,the through holes 21 are arranged so as not to overlap the semiconductorelement 12 in a planar view. The part of the stress relaxation member 20that is directly below the semiconductor element 12 is closest to thesemiconductor element 12, and serves as a thermally conductive portion22, which has a better thermal conductivity than the through holes 21.

Operation of the semiconductor device 10A will now be described.

The semiconductor device 10A of the present embodiment is mounted on ahybrid vehicle, and the heat sink 16 is connected to a cooling mediumcircuit (not shown) of the vehicle through pipes. The cooling mediumcircuit has a pump and a radiator. The radiator has a fan that is drivenby a motor. The radiator thus has a superior radiation efficiency. Thecooling medium is, for example, water.

When the semiconductor element 12 mounted on such a semiconductor device10A is actuated, the semiconductor element 12 generates heat. The heatgenerated in the semiconductor element 12 is conducted to the heat sink16 through the first metal plate 14, the ceramic substrate 13, thesecond metal plate 15, the stress relaxation member 20, and the heatsink 16. The part of the stress relaxation member 20 that is directlybelow the semiconductor element 12 is the thermally conductive portion22, which has no through hole 21. Thus, the heat transmitted to thestress relaxation member 20 is smoothly conducted to the heat sink 16.

As a result, the circuit substrate 11 and the heat sink 16 are heated tohigh temperature and thermally expanded. At this time, if through holesformed in the stress relaxation member 20 are like a hypothetic hole R1,which is shown by an alternate long and two short dashes line in FIG. 2and formed like a perfect circle, the stress due to thermal expansiongenerated along the longitudinal direction of the partitioning walls 18in a part between the heat sink 16 and the ceramic substrate 13 isgreater than the stress due to the thermal expansion generated along thearranging direction of the partitioning walls 18. That is, since thecoefficient of linear expansion of the ceramic substrate 13 and thecoefficient of linear expansion of the metal members (the heat sink 16and the first and second metal plates 14, 15) are different, thermalstress is generated in the semiconductor device 10A. Particularly, agreat thermal stress along the longitudinal direction of thepartitioning walls 18 is generated between the heat sink 16 and theceramic substrate 13. If the through holes are enlarged like ahypothetical hole R2 in order to relax the thermal stress along thelongitudinal direction of the partitioning walls 18, the joint areabetween the stress relaxation member 20 and the heat sink 16 will bereduced, and the thermal conductivity of the stress relaxation member 20will therefore be lowered. The shape of the through holes 21 in thepresent embodiment is determined taking into consideration the arrangingdirection of the partitioning walls 18 of the heat sink 16. Since thestress relaxation member 20 of the present embodiment is more easilydeformed in the longitudinal direction of the partitioning walls 18 thanin the arranging direction of the partitioning walls 18, the stressrelaxation member 20 thus more effectively relaxes the thermal stress inthe longitudinal direction of the partitioning walls 18 than the thermalstress in the arranging direction. As a result, the thermal stress alongthe longitudinal direction of the partitioning walls 18 is equalizedwith the thermal stress along the arranging direction. Therefore, thethrough holes do not need to be enlarged more than necessary. Thisprevents the thermal conductivity of the stress relaxation member 20from being lowered. Further, when the temperature of the semiconductordevice 10A is raised, it is possible to inhibit the joint portionsbetween the ceramic substrate 13 and the second metal plate 15 fromcracking, and the joint surface of the heat sink 16 that faces thecircuit substrate 11 from warping.

When the semiconductor element 12 stops generating heat, the temperatureof the ceramic substrate 13 and the heat sink 16 is lowered, and theceramic substrate 13 and heat sink 16 are thermally shrunk. At thistime, since the stress relaxation member 20 is more easily deformed inthe longitudinal direction of the partitioning walls 18 than in thearranging direction of the partitioning walls 18, the thermal stressbetween the heat sink 16 and the second metal plate 15 is relaxed by agreater degree along the longitudinal direction of the partitioningwalls 18 than along the arranging direction of the partitioning walls18. Therefore, when the temperature of the semiconductor device 10A islowered, it is possible to inhibit the joint portions between theceramic substrate 13 and the second metal plate 15 from cracking, andthe joint surface of the heat sink 16 that faces the circuit substrate11 from warping.

Also, when the heat generated in the semiconductor element 12 isconducted to the heat sink 16, heat exchange takes place between thecooling medium flowing through the cooling medium passages 19, and thecase portion 17 and the partitioning walls 18, so that the heat isremoved by the cooling medium. That is, since the heat sink 16 isforcibly cooled by the cooling medium flowing through the cooling mediumpassages 19, the temperature gradient of the conduction path of heatfrom the semiconductor element 12 to the heat sink 16 is increased. Thisallows the heat generated in the semiconductor element 12 to beefficiently removed through the circuit substrate 11.

The present embodiment has the following advantages.

(1) The stress relaxation member 20 has a plurality of through holes 21.The dimension T1 of each through hole 21 along the longitudinaldirection of the partitioning walls 18 is greater than the dimension T2of the through hole 21 along the arranging direction of the partitioningwalls 18. Therefore, the stress relaxation member 20 is more easilydeformed in the longitudinal direction of the partitioning walls 18 thanin the arranging direction of the partitioning walls 18. As a result,the thermal stress along the longitudinal direction of the partitioningwalls 18 is equalized with the thermal stress along the arrangingdirection.

(2) The dimension T2 of each through holes 21 along the arrangingdirection of the partitioning walls 18 is shorter than the dimension T1along the longitudinal direction of the partitioning walls 18. Thus,compared to the case where the hypothetical hole R1 is enlarged to thehypothetical hole R2 in order to improve the stress relaxationperformance of the stress relaxation member 20, the joint area betweenthe heat sink 16 and the stress relaxation member 20 is inhibited frombeing reduced. Therefore, the heat generated in the semiconductorelement 12 is smoothly conducted through the stress relaxation member 20and reaches the heat sink 16. This prevents the thermal conductivity ofthe stress relaxation member 20 from being lowered.

(3) The second metal plate 15 is joined to the back surface 13 b of theceramic substrate. The stress relaxation member 20, which is a separatecomponent from the circuit substrate 11, is provided between the heatsink 16 and the second metal plate 15 of the circuit substrate 11.Therefore, the stress relaxation member 20 is manufactured independentlyfrom the semiconductor element 12 and the ceramic substrate 13. Thethrough holes 21 of the stress relaxation member 20 are easily formedby, for example, machining such as pressing a plate member. Therefore,when forming the through holes 21, the influence on the semiconductorelement 12 and the ceramic substrate 13 does not need to be taken intoconsideration.

(4) A part of the stress relaxation member 20 that is directly below thesemiconductor element 12 serves as the thermally conductive portion 22,through which the heat generated in the semiconductor element 12 passes,and the thermally conductive portion 22 has no through holes 21. Thatis, a part of the stress relaxation member 20 to which the heatgenerated in the semiconductor element 12 reaches first is formed as thethermally conductive portion 22 having no through holes 21. Therefore,the heat generated in the semiconductor element 12 is smoothly conductedthrough the stress relaxation member 20 and reaches the heat sink 16.

(5) The through holes 21 extend along the thickness of the stressrelaxation member 20. Therefore, compared to a case where a stressrelaxation member is manufactured by forming a plurality of bottomedholes in a plate member made of a material having a high thermalconductivity, the stress relaxation member 20 is formed to be moreeasily deformed.

The first embodiment is not limited to the above describedconfiguration, but may be embodied as follows, for example.

The major axis of the through holes 21 do not need to be parallel withthe longitudinal direction of the partitioning walls 18. it issufficient if the dimension T1 along the longitudinal direction of thepartitioning walls 18 is longer than the dimension T2 along thearranging direction of the partitioning walls 18. For example, ellipticthrough holes may be formed that has a major axis intersecting thelongitudinal direction of the longitudinal direction of the partitioningwalls 18.

The number of the through holes 21 is not limited to that according tothe first embodiment. When a large sized stress relaxation member 20 isused, the number of through holes 21 may be increased.

The shape of the through holes 21 may be changed. The size of thethrough holes 21 may be reduced or increased as long as the dimension T1along the longitudinal direction of the partitioning walls 18 is longerthan the dimension T2 along the arranging direction of the partitioningwalls 18. Therefore, for example, through holes 21 may be formed inwhich the dimension T2 along the arranging direction of the partitioningwalls 18 is longer than the diameter of the hypothetical hole R1.

The shape of the through holes 21 is not limited to that according tothe first embodiment. For example, as shown in FIG. 3A, through holes 30that have a rectangular shape in a planar view may be formed. Adimension T3 of each through hole 30 along the longitudinal direction ofthe partitioning walls 18 is longer than a dimension T4 along thearranging direction of the partitioning walls 18. Also, as shown in FIG.3B, through holes 31 may be formed by connecting each set of the throughholes 30 shown in FIG. 3A along the longitudinal direction of thepartitioning walls 18. In this case, a part of the stress relaxationmember 20 that is directly below the semiconductor element 12 needs tobe formed as a thermally conductive portion 22, where no through hole 31exists.

Each stress absorbing portion may be a group of holes, in which holesextend through the thickness of the stress relaxation member 20 and arearranged along the longitudinal direction of the partitioning walls 18.For example, as shown in FIG. 3C, each through hole 21 of the stressrelaxation member 20 may be replaced by a group of holes 40. Each groupof holes 40 includes a plurality of holes 41 (three in FIG. 3C). Eachthrough hole 41 is rectangular such that its opening dimension t1 alongthe longitudinal direction of the partitioning walls 18 is shorter thanits dimension t2 along the arranging direction of the partitioning walls18. The through holes 41 forming each group of holes 40 are arrangedalong the longitudinal direction of the partitioning walls 18. Eachgroup of holes 40 is formed such that the sum of the dimensions t1 alongthe longitudinal direction of the partitioning walls 18 is greater thanthe dimension t2 of each through hole 41 (the dimension of the stressabsorbing portion) along the arranging direction of the partitioningwalls 18. Also, the distance H1 between adjacent groups of holes 40along the longitudinal direction of the partitioning walls 18 is greaterthan the distance H2 between adjacent holes 41 in each group of hole 40along the longitudinal direction of the partitioning walls 18. Since thestress relaxation member 20 having a plurality of the groups of holes 40is easily deformed in the longitudinal direction of the partitioningwalls 18, the stress relaxation member 20 effectively relaxes thethermal stress along the longitudinal direction of the partitioningwalls 18, which improves the stress relaxation performance. Further,since each stress absorbing portion is formed by a group of holes 40,which includes through holes 41 extending through the thickness of thestress relaxation member 20, the stress relaxation member 20 is moreeasily and effectively deformed than a stress absorbing portion formedby bottomed holes. Also, as long as the maximum value of the length(dimension) of each group of holes 40 along the arranging direction ofthe partitioning walls 18 is less than the sum the dimensions t1 alongthe longitudinal direction of the partitioning walls 18, the throughholes 41 in each group of holes 40 may be arranged along thelongitudinal direction of the partitioning walls 18 while being slightlydisplaced in the arranging direction of the partitioning walls 18.

The positions of the through holes 21 on the stress relaxation member 20are not limited to those according to the first embodiment. For example,the through holes 21 may be arranged zigzag.

The through holes 21 as stress absorbing portions may be replaced bybottomed holes, each having an opening only on one of the surfaces ofthe stress relaxation member 20 in the direction of thickness. Thelength (opening dimension) of each bottomed hole along the longitudinaldirection of the partitioning walls 18 may be set arbitrarily as long asit is longer than the length (opening dimension) along the arrangingdirection of the partitioning walls 18. The bottomed holes may open, forexample, in the second surface 20 b of the stress relaxation member 20.When bottomed holes are formed in the stress relaxation member 20instead of through holes 21, the depth of the bottomed holes is notparticularly limited as long as the stress relaxation member 20sufficiently relaxes thermal stress generated in the semiconductordevice 10A.

The second metal plate 15 may also function as the stress relaxationmember 20. For example, the stress relaxation member 20 may be omitted,and a plurality of holes may be formed in a surface of the second metalplate 15 that faces the heat sink 16. The dimension of each hole alongthe longitudinal direction of the partitioning walls 18 is longer thanthe dimension along the arranging direction of the partitioning walls18. According to this configuration, the second metal plate 15 functionsas a stress relaxation member that relaxes thermal stress generated inthe semiconductor device 10A when the temperature of the semiconductordevice 10A changes. Also, since the second metal plate 15 can be greatlydeformed in the longitudinal direction of the partitioning walls 18compared to a conventional stress relaxation member having a stressabsorbing portions formed by perfect-circle shaped holes in a planarview, the second metal plate 15 has an improved stress relaxationperformance.

The direction in which the partitioning walls 18 extend is not limitedto that in the first embodiment. As long as the partitioning walls 18extend in a single direction, the extending direction is notparticularly limited. For example, the partitioning walls 18 may extendin a direction intersecting the transverse direction of the heat sink16.

The partitioning walls 18 may be continuous along the arrangingdirection. For example, corrugated fins may be used in which a pluralityof partitioning walls 18 are continuously formed in the arrangingdirection of the partitioning walls 18. In corrugated fins, the upperends or the lower ends of each adjacent pair of the partitioning walls18 are continuous.

The structure of the heat sink 16 is not limited to that described inthe first embodiment. For example, the case portion 17 may be replacedby a plate-like heat sink base. The heat sink base has a first surfaceopposite to the semiconductor element 12, and a second surface oppositeto the first surface. The heat sink base has a plurality of partitioningwalls 18 on the first surface, and the stress relaxation member 20 isjoined to the second surface.

A second embodiment of the present invention will now be described withreference to FIGS. 4 to 7. The differences from the first embodimentwill mainly be discussed below. Each of the FIGS. 4 to 7 schematicallyshows the structure of a semiconductor device 10B according to thesecond embodiment. For the illustrative purposes, the dimensions of someof the elements are exaggerated. That is, the ratios of the widths,lengths, and thicknesses of some of the elements of the semiconductordevice 10B in the drawings are not to scale. The semiconductor device10B is mounted on a vehicle.

In a heat sink 16 of the present embodiment, a front surface 17 a of acase portion 17 includes a joint region S, to which a second metal plate15 is joined by brazing filler metal (not shown), and a non-joint regionP encompassing the joint region S. The second metal plate 15 is notjoined to the non-joint region P. The case portion 17 has a back surface17 b on the opposite side to the front surface 17 a. Linearly extendingstraight first partitioning walls 18A and second partitioning walls 18Bare formed in the case portion 17 of the present embodiment.

The first partitioning walls 18A and the second partitioning walls 18Bare arranged at equal intervals along the longitudinal direction of theheat sink 16, or along arrow direction X in FIG. 4, and are parallelwith each other. Adjacent pairs of the first and second partitioningwalls 18A and 18B, and the outermost second partitioning walls 18B andinner wall surfaces 17 c of the case portion 17 define cooling mediumpassages 19, through which cooling medium flows. The cooling mediumpassages 19 are formed to have the same cross-sectional flow area.

The first partitioning walls 18A are located in a region in the caseportion 17 that is directly below the joint region S in the laminationdirection (arrow direction Z in FIG. 5), and in a region in the caseportion 17 that corresponds to the non-joint region P (hereinafter, afirst non-joint region P1), which extends from the joint region S alongthe extending direction of the partitioning walls 18A, 18B (arrowdirection Y in FIG. 5). Each first partitioning wall 18A has an upperend 18Aa, which is a first end, at a side closer to the semiconductorelement 12. Each upper end 18Aa is joined to an upper inner surface 17 dof the case portion 17. As shown in FIGS. 4 and 5, each firstpartitioning wall 18A has a lower end 18Ab, which is a second end, at aside opposite to the first end. The lower end 18Ab of each firstpartitioning wall 18A contacts but is not joined to the lower innersurface 17 e of the case portion 17 over the extending direction of thefirst partitioning walls 18A, that is, over arrow direction Y in FIG. 5.That is, only the first partitioning walls 18A exist in a region in thecase portion 17 that is directly below the joint region S. The upper end18Aa of each first partitioning wall 18A and the upper inner surface 17d of the case portion 17 are joined by brazing filler metal (not shown).Contrastingly, no brazing filler metal exists between the lower end 18Abof each first partitioning wall 18A and the lower inner surface 17 e ofthe case portion 17. That is, the lower end 20 b and the lower innersurface 17 e are not joined to each other.

Also, as shown FIG. 4, all the second partitioning walls 18B are locatedin a region in the case portion 17 that corresponds to a secondnon-joint region P2, which is a region other than the regions S, P1. Theupper end 18Ba of each second partitioning wall 18B and the upper innersurface 17 d of the case portion 17 are joined by brazing filler metal(not shown). Also, the lower end 18Bb of each second partitioning wall18B and the lower inner surface 17 e of the case portion 17 are joinedby brazing filler metal (not shown). The cooling medium passages 19,which are defined by the first partitioning walls 18A and the secondpartitioning walls 18B, connect an inlet and outlet (neither is shown)provided in the case portion 17. The inlet and outlet are formed to beconnectable with a cooling medium circuit installed in the vehicle. Forthe illustrative purpose, the circuit substrate 11 and the semiconductorelement 12 exemplify multiple circuit substrates 11 and semiconductorelements 12 mounted on the heat sink 16.

Operation of the semiconductor device 10B will now be described.

The semiconductor device 10B is mounted on a hybrid vehicle, and theheat sink 16 is connected to a cooling medium circuit (not shown) of thevehicle through pipes. The cooling medium circuit has a pump and aradiator. The radiator has a fan that is driven by a motor. The radiatorthus has a superior radiation efficiency. The cooling medium is, forexample, water.

When the semiconductor element 12 mounted on the semiconductor device10B is actuated, heat is generated from the semiconductor element 12.The heat generated in the semiconductor element 12 is conducted to theheat sink 16 through the first metal plate 14, the ceramic substrate 13,the second metal plate 15, and the heat sink 16. When the heat isconducted from the semiconductor element 12 to the heat sink 16, thecircuit substrate 11 and the heat sink 16 are heated to high temperatureand thermally expanded. At this time, since the coefficient of linearexpansion of the ceramic substrate 13 and the coefficient of linearexpansion of the metal members (the heat sink 16 and the first andsecond metal plates 14, 15) are different, the amount of expansion isdifferent between the heat sink 16, and the first and second metalplates 14, 15. However, the heat sink 16 is deformed to relax thethermal stress generated in the semiconductor device 10B. Further, sincethe rigidity of the portion of the heat sink 16 of the presentembodiment that corresponds to the joint region S is particularly low,the portion that corresponds to the joint region S is particularlyeasily deformed. As a result, the heat sink 16 sufficiently relaxes thethermal stress generated in the semiconductor device 10B. Therefore,when the temperature of the ceramic substrate 13 and heat sink 16increases, it is possible to inhibit the joint portions between theceramic substrate 13 and the second metal plate 15 from cracking, andthe joint surface of the heat sink 16 that faces the circuit substrate11 from warping.

When the semiconductor element 12 stops generating heat, the temperatureof the ceramic substrate 13 and the heat sink 16 is lowered, and theceramic substrate 13 and heat sink 16 are thermally shrunk. At thistime, being easily deformed, the heat sink 16 relaxes the thermal stressgenerated in the semiconductor device 10B. Therefore, when thetemperature of the ceramic substrate 13 and heat sink 16 lowers, it ispossible to inhibit the joint portions between the ceramic substrate 13and the second metal plate 15 from cracking, and the joint surface ofthe heat sink 16 that faces the circuit substrate 11 from warping.

Also, when the heat generated in the semiconductor element 12 isconducted to the heat sink 16, heat exchange takes place between thecooling medium flowing through the cooling medium passages 19 and thecase portion 17, and between the cooling medium and the first and secondpartitioning walls 18A, 18B, so that the heat is removed by the coolingmedium. That is, since the heat sink 16 is forcibly cooled by thecooling medium flowing through the cooling medium passages 19, thetemperature gradient of the conduction path of heat from thesemiconductor element 12 to the heat sink 16 is increased. This allowsthe heat generated in the semiconductor element 12 to be efficientlyremoved through the circuit substrate 11.

The first partitioning walls 20 hardly contribute to improve therigidity of the heat sink 16. If partition walls having the samestructure as the first partitioning walls 18A are arranged in a regionin the case portion 17 that corresponds to the second non-joint regionP2, the rigidity of the heat sink 16 will be lower than a predeterminedacceptable value, and therefore, the shape of the case portion 17 cannotbe maintained. However, according to the present embodiment, the upperend 18Ba and the lower end 18Bb of each of the partitioning walls 18B ina region of the case portion 17 that corresponds to the second non-jointregion P2 are joined to the inner surfaces 17 d, 17 e of the caseportion 17. Since the second partitioning walls 18B have a function toinhibit deformation of the case portion 17, the rigidity of the heatsink 16 is inhibited from being excessively lowered. The rigidity of theheat sink 16 is therefore maintained to an appropriate level. As aresult, although the rigidity of the heat sink 16 is lowered as much aspossible in the allowable range so that the heat sink 16 exerts asufficient thermal stress relaxation performance, the rigidity is notexcessively lowered to a detrimental level.

The present embodiment has the following advantages.

(1) The first partitioning walls 18A, which serve as partitioning walls,are located in a region in the case portion 17 that corresponds to thejoint region S. The second partitioning walls 18B are located in aregion in the case portion 17 that corresponds to the second non-jointregion P2 in the non-joint region P. Therefore, compared to a heat sinkin which partitioning walls are located only in the joint region S andthe first non-joint region P1, that is, compared to a heat sink in whichno partitioning walls are located in the second non-joint region P2, theheat sink 16 has a lower rigidity. As a result, the thermal stressgenerated in the semiconductor device 10B is relaxed.

(2) The upper end 18Ba and the lower end 18Bb of each of the secondpartitioning walls 18B, which are only provided in a region in the caseportion 17 that corresponds to the second non-joint region P2, are bothjoined to the inner surface of the case portion 17. Therefore, therigidity of the heat sink 16 is not excessively lowered.

(3) The upper end 18Aa of each first partitioning wall 18A is joined tothe upper inner surface 17 d of the case portion 17, whereas the lowerend 20 b of each first partitioning wall 18A is not joined to the lowerinner surface 17 e of the case portion 17. Therefore, a portion of theheat sink 16 that corresponds to the joint region S and the firstnon-joint region P1 has a lower rigidity than a portion that correspondsto the second non-joint region P2. As a result, since a part of thejoint region S of the heat sink 16 that is close to the ceramicsubstrate 13 is more easily deformed than the second non-joint regionP2, thermal stress due to the difference in the coefficient linearexpansion between the ceramic substrate 13 and the heat sink 16 iseffectively relaxed.

(4) A partitioning wall that passes through a region in the case portion17 that corresponds to the second non-joint region P2 is only the secondpartitioning walls 18B. Therefore, the rigidity of the heat sink 16 iseffectively prevented from being excessively lowered.

(5) All the partition walls that pass through the joint region S and thefirst non-joint region P1 are the first partitioning walls 18A.Therefore, compared to a case where, for example, second partitioningwalls 18B is provided in the joint region S in addition to firstpartitioning walls 18A, the rigidity of the heat sink 16 is furtherlowered.

(6) The lower end 20 b of each first partitioning walls 18A directlycontacts the lower inner surface of the case portion 17. Therefore, theheat transmitted to the first partitioning walls 18A can be transmittedfrom the lower ends 20 b to the case portion 17. This allows the heat tobe smoothly transmitted to the entire heat sink 16.

The second embodiment is not limited to the above describedconfiguration, but may be embodied as follows, for example.

It is sufficient if only a part of the lower end 20 b of each firstpartitioning wall 18A that is directly below the joint region S is notjoined to the lower inner surface 17 e of the case portion 17. Forexample, it may be configured that, in each first partitioning wall 18A,only the lower end 20 b, which is directly below the joint region S, isnot joined to the lower inner surface 17 e of the case portion 17, andthat the lower end 20 b that is directly below first non-joint region P1contacts the lower inner surface 17 e of the case portion 17.

The partitioning walls that pass through a region in the case portion 17that corresponds to the joint region S and the first non-joint region P1do not need to be only the first partitioning walls 18A. For example, asshown in FIG. 6, first partitioning walls 50, of which the lower ends 20b are not joined to the lower inner surface 17 e of the case portion 17,and second partitioning walls 51, of which the lower ends 20 b arejoined to the lower inner surface 17 e of the case portion 17, may beprovided in a mixed state in a region in the case portion 17 thatcorresponds to joint region S. In this case, the first partitioningwalls 50 and the second partitioning walls 51 may be arrangedalternately at predetermined intervals.

The extending direction of the first partitioning walls 18A is notlimited to that described in the second embodiment. For example, thefirst partitioning walls 18A may be parallel with the longitudinaldirection of the heat sink 16, that is, parallel with arrow direction Xin FIG. 4. Also, the extending direction of the second partitioningwalls 18B may be parallel with the longitudinal direction of the heatsink 16.

The first partitioning walls 18A may be continuous along the arrangingdirection. Also, the second partitioning walls 18B may be continuousalong the arranging direction. The first partitioning walls 18A and thesecond partitioning walls 18B may be continuous along the arrangingdirection. Therefore, for example, corrugated fins may be used to formfirst fins, which serve as the first partitioning walls 18A, and secondfins, which serve as the second partitioning walls 18B. The corrugatedfins connected such that the upper end of each first fin is continuouswith the upper end of an adjacent first fin, and that the lower end ofeach first fin is continuous with the lower end of an adjacent firstfin. Likewise, the upper end of each second fin is continuous with theupper end of an adjacent second fin, and the lower end of each secondfin is continuous with the lower end of an adjacent second fin.

As shown in FIG. 7, the stress relaxation member 20 of the firstembodiment may be located between the second metal plate 15 and the heatsink 16.

In the heat sink 16, the joint portions between the case portion 17 andthe first and second partitioning walls 18A, 18B, 50, 51 are brazed.However, the heat sink 16 may be formed by extrusion molding.

The lower ends 20 b, 50 b of the first partitioning walls 18A, 50 do notneed to contact the inner surface 17 e. However, in view of betterthermal conductivity, the lower ends 20 b, 50 b of the firstpartitioning walls 18A, 50 preferably contact the inner surface 17 e.

A third embodiment of the present invention will now be described withreference to FIGS. 8 to 10B. The differences from the first embodimentwill mainly be discussed below. Each of the FIGS. 8 to 10B schematicallyshows the structure of a semiconductor device 10C according to the thirdembodiment. For the illustrative purposes, the dimensions of some of theelements are exaggerated. That is, the ratios of the widths, lengths,and thicknesses of some of the elements of the semiconductor device 10Cin the drawings are not to scale. The semiconductor device 10C ismounted on a vehicle.

As shown in FIGS. 8 and 9, partitioning walls 18 of the presentembodiment are formed to pass through regions directly below a pluralityof semiconductor elements 12. The semiconductor elements 12 includesemiconductor elements 12A that are located on the left side as viewedin FIG. 9 and linearly arranged in the vertical direction as viewed inFIG. 9. The partitioning walls 18 include three first partitioning walls18A located in a region directly below the semiconductor elements 12 A.Likewise, semiconductor elements 12B are located on the right side asviewed in FIG. 9 and linearly arranged in the vertical direction asviewed in FIG. 9. The partitioning walls 18 include three secondpartitioning walls 18B located in a region directly below thesemiconductor elements 12B. The first partitioning walls 18A and thesecond partitioning walls 18B are arranged at equal intervals. In thepresent embodiment, a region “directly below the semiconductor elements12” refers to a region that overlaps the semiconductor elements 12 whenviewed from above. Therefore, it does not include regions that are lowerthan the semiconductor element 12 but outside the edges of thesemiconductor elements 12.

Portion of each partitioning wall 18 that are directly below thecorresponding semiconductor elements 12 are referred to as correspondingportions Q. Each corresponding portion Q receives the heat generated inthe corresponding semiconductor element 12 in a concentrated manner. Allthe regions that are directly below the semiconductor elements 12 havecorresponding portions Q. Cooling medium passages 19, which are definedby the partitioning walls 18, connect an inlet and outlet (neither isshown) provided in the case portion 17. The inlet and outlet are formedto be connectable with a cooling medium circuit installed in thevehicle.

Operation of the semiconductor device 10C will now be described.

The semiconductor device 10C is mounted on a hybrid vehicle, and theheat sink 16 is connected to a cooling medium circuit (not shown) of thevehicle through pipes. The cooling medium circuit has a pump and aradiator. The radiator radiates the heat of the cooling medium. Thecooling medium is, for example, water.

When the semiconductor element 12 mounted on the semiconductor device10C is actuated, heat is generated from the semiconductor element 12.The heat generated in the semiconductor element 12 is conducted to theheat sink 16 through the first metal plate 14, the ceramic substrate 13,the second metal plate 15, and the heat sink 16 as shown by arrows A inFIG. 8. When the heat is conducted from the semiconductor elements 12 tothe heat sink 16, the circuit substrates 11 and the heat sink 16 areheated to high temperature and thermally expanded. At this time, sincethe coefficient of linear expansion of the ceramic substrate 13 and thecoefficient of linear expansion of the metal members (the heat sink 16and the first and second metal plates 14, 15) are different, the amountof expansion of the ceramic substrate 13 is different from that of theheat sink 16 and the first and second metal plates 14, 15. Thisgenerates thermal stress in the semiconductor device 10C. Since the heatsink 16 has no partitioning walls other than the partitioning walls 18,which pass through the region directly below the semiconductor elements12, the number of partitioning walls that restrict deformation of thecase portion 17 is small. Accordingly, the ratio of the volume of thepartitioning walls 18 is small in the case portion 17. Therefore,compared to a heat sink that has, in addition to the partitioning walls18, partitioning walls that have the same structure as the partitioningwalls 18 and are located in regions other than regions directly belowthe semiconductor elements 12, the heat sink 16 is more easily deformedso that the thermal stress generated in the semiconductor device 10C iseffectively relaxed. As a result, when the temperature of the circuitsubstrates 11 and heat sink 16 increases, it is possible to inhibit thejoint portions between the ceramic substrates 13 and the second metalplates 15 from cracking, and the joint surface of the heat sink 16 thatfaces the circuit substrates 11 from warping.

When the heat generated in the semiconductor elements 12 is transmittedto the heat sink 16, the heat is first transmitted in a concentratedmanner to parts of the case portion 17 that are directly below thesemiconductor elements 12 and the corresponding parts Q of thepartitioning walls 18. The heat is thereafter transmitted to the entireheat sink 16. In each of the regions directly below the semiconductorelements 12, the partitioning walls 18 allow effective heat exchange totake place with the cooling medium, so that the heat transmitted to thecase portion 17 and the partitioning walls 18 are smoothly removed. Thatis, since the heat sink 16 is forcibly cooled by the cooling mediumflowing through the cooling medium passages 19, the temperature gradientof the conduction path of heat from the semiconductor element 12 to theheat sink 16 is increased. This allows the heat generated in thesemiconductor element 12 to be efficiently removed through the circuitsubstrate 11.

When the semiconductor element 12 stops generating heat, the temperatureof the circuit board 11 and the heat sink 16 is lowered, and the circuitboard 11 and the heat sink 13 are thermally shrunk. At this time, beingeasily deformed, the heat sink 16 relaxes the thermal stress generatedin the semiconductor device 100. Therefore, when the temperature of thecircuit substrates 11 and heat sink 16 lowers, it is possible to inhibitthe joint portions between the ceramic substrates 13 and the secondmetal plates 15 from cracking, and the joint surface of the heat sink 16that faces the circuit substrates 11 from warping.

The present embodiment has the following advantages.

(1) In the case portion 17, the partitioning walls 18 are each locatedto pass through a region directly below one of the semiconductorelements 12, and no partition wall is provided in regions other thanregions directly below the semiconductor elements 12. Therefore, thenumber of partitioning walls that restrict deformation of the caseportion 17 is reduced, so that the ratio of the volume of thepartitioning walls 18 in the case portion 17 is reduced. This lowers therigidity of the heat sink 16, so that the stress relaxation performanceof the heat sink 16 is improved.

(2) The partitioning walls 18 exist in each region directly below thesemiconductor elements 12. Therefore, heat is effectively radiated fromthe region directly below each semiconductor element 12.

(3) The partitioning walls 18 are arranged to pass through the regionsdirectly below the linearly arranged semiconductor elements 12.Therefore, compared to a case where a single partitioning wall isprovided to correspond to each semiconductor element 12 so as to passthrough a region directly below the semiconductor element 12, the numberof the partitioning walls 18 in the heat sink 16 is reduced. Thissimplifies the structure of the heat sink 16.

The third embodiment is not limited to the above describedconfiguration, but may be embodied as follows, for example.

The number of the partitioning walls 18 in the case portion 17 may bechanged. As long as all the partitioning walls 18 are each arranged topass through one of the region directly below the first semiconductorelements 12A and the region directly below the second semiconductorelements 12B, the number of the partitioning walls 18 may be increasedor decreased. However, when increasing the number of the partitioningwalls 18, the number of the partitioning walls 18 needs to set within arange that allows the heat sink 16 to sufficiently exert its stressrelaxation performance.

The partitioning walls 18 may be integrated. For example, the threepartitioning walls 18 on the left side in FIG. 8 may be formed bycorrugated fins located in a region directly below the firstsemiconductor elements 12A. Likewise, the three partitioning walls 18 onthe right side in FIG. 8 may be formed by corrugated partitioning plateslocated in a region directly below the first semiconductor elements 12B.

The shape of the partitioning walls 18 is not limited to that accordingto the third embodiment. Instead of linearly extending partitioningwalls, zigzag partitioning walls 60 shown in FIG. 10A may be provided.This structure disturbs the flow of cooling medium flowing between thepartitioning walls 60. Thus, compared to the case of linearly extendingpartitioning walls, the cooling performance is improved.

In place of the continuously extending partitioning walls 18,discontinuous partitioning walls 18 having wall segments may beprovided. For example, each discontinuous partitioning wall 18 has a gapof a predetermined length in a region outside the region directly belowthe semiconductor element 12 and has wall segments that continues afterthe gap.

It may be configured such that a single partitioning wall 18 passesthrough a region directly below a single semiconductor element 12. Forexample, a plurality of semiconductor elements 12 may be arranged in aline, and partitioning walls 18 extending in one direction may beprovided such that each partitioning wall 18 corresponds to one of thesemiconductor elements 12. In this case, each partitioning wall 18separately passes through a region directly below one of thesemiconductor elements 12. Alternatively, as shown in FIG. 10B, aplurality of fins 70 (partitioning walls), which are cross-shaped in aplanar view, may be provided to correspond to each semiconductor element12, such that fins located in a region directly below each semiconductorelement 12 are independent from each other. Compared to a case wherepartitioning walls 18 that continuously extend in one direction, coolingmedium is more greatly disturbed, so that the cooling performance isimproved. Also, the cooling performance is not easily influenced by theflow of cooing medium.

The number of the semiconductor elements 12 on the circuit substrate 11is not particularly limited. Two or more semiconductor elements 12 maybe mounted on a single circuit substrate 11.

A stress relaxation member as described in the first embodiment may belocated between each second metal plate 15 and the heat sink 16.

The above described embodiments may be modified as follows.

The material for forming the heat sink 16 may be any metal that has acoefficient of linear expansion different from that of the ceramicsubstrate 13. For example, the heat sink 16 may be made of aluminum orcopper. Aluminum refers to pure aluminum and aluminum alloys.

The material for forming the ceramic substrate 13 is not particularlylimited. The ceramic substrate 13 may be formed, 30 for example, ofaluminum nitride, alumina, or silicon nitride.

In the illustrated embodiments, water flows through the heat sink 16.However, liquid other than water, such as alcohol, may flow through theheat sink 16. The cooling medium that flows through the heat sink 16 isnot limited to liquid, but may be gas such as air.

The semiconductor devices 10A, 10B, 10C do not need to be installed onvehicles but may be applied to other uses.

What is claimed:
 1. A semiconductor device comprising: an insulationsubstrate having a first surface and a second surface that is oppositeto the first surface; a metal wiring layer joined to the first surfaceof the insulation substrate; a semiconductor element joined to the metalwiring layer; a heat sink arranged on the second surface of theinsulation substrate; and a stress relaxation member made of a materialhaving a high thermal conductivity, the stress relaxation member beinglocated between the insulation substrate and the heat sink in suchmanner as to couple the insulation substrate and the heat sink such thatheat can be conducted therebetween, wherein the heat sink has aplurality of partitioning walls that extend in one direction and arearranged at intervals, wherein the stress relaxation member has a stressabsorbing portion that is formed by a through hole, the through holeextending through the entire thickness of the stress relaxation member,and wherein the through hole is a rectangular hole having a long side,which extends along the longitudinal direction of the partitioningwalls, and a short side, which extends along the arranging direction ofthe partitioning walls, such that its dimension along the longitudinaldirection of the partitioning walls is greater than its dimension alongthe arranging direction of the partitioning walls to equalize thethermal stress along the longitudinal direction of the partitioningwalls with the thermal stress along the arranging direction of thepartitioning walls.
 2. The semiconductor device according to claim 1,wherein a metal plate is joined to the second surface, and wherein thestress relaxation member is formed separately from the metal plate. 3.The semiconductor device according to claim 1, wherein a portion of thestress relaxation member that corresponds to the semiconductor elementdoes not have the stress absorbing portion, so as to function as athermally conductive portion, to which heat generated in thesemiconductor element can be conducted.
 4. A semiconductor devicecomprising: an insulation substrate having a first surface and a secondsurface that is opposite to the first surface; a metal wiring layerjoined to the first surface of the insulation substrate; a semiconductorelement joined to the metal wiring layer; a heat sink arranged on thesecond surface of the insulation substrate; and a stress relaxationmember made of a material having a high thermal conductivity, the stressrelaxation member being located between the insulation substrate and theheat sink in such manner as to couple the insulation substrate and theheat sink such that heat can be conducted therebetween, wherein the heatsink has a plurality of partitioning walls that extend in one directionand are arranged at intervals, wherein the stress relaxation member hasa stress absorbing portion that is formed by a plurality of throughholes, the through holes extending through the entire thickness of thestress relaxation member, and wherein each of the through holes is arectangular hole having a long side, which extends along thelongitudinal direction of the partitioning walls, and a short side,which extends along the arranging direction of the partitioning walls,such that its dimension along the longitudinal direction of thepartitioning walls is greater than its dimension along the arrangingdirection of the partitioning walls to equalize the thermal stress alongthe longitudinal direction of the partitioning walls with the thermalstress along the arranging direction of the partitioning walls.
 5. Asemiconductor device comprising: an insulation substrate having a firstsurface and a second surface that is opposite to the first surface; ametal wiring layer joined to the first surface of the insulationsubstrate; a semiconductor element joined to the metal wiring layer; aheat sink arranged on the second surface of the insulation substrate;and a stress relaxation member made of a material having a high thermalconductivity, the stress relaxation member being located between theinsulation substrate and the heat sink in such manner as to couple theinsulation substrate and the heat sink such that heat can be conductedtherebetween, wherein the heat sink has a plurality of partitioningwalls that extend in one direction and are arranged at intervals,wherein the stress relaxation member has a stress absorbing portion, thestress absorbing portion including a group of through holes extendingthrough the entire thickness of the stress relaxation member, thethrough holes being arranged along the longitudinal direction of thepartitioning walls, wherein each of all the through holes of the groupis formed such that its opening dimension along the arranging directionof the partitioning walls is greater than its opening dimension alongthe longitudinal direction of the partitioning walls, and wherein thesum of the opening dimensions of all the through holes of the groupalong the longitudinal direction of the partitioning walls is longerthan the maximum width of the through holes of the group along thearranging direction of the partitioning walls.